The present invention relates to a method for improving characteristics of parasitic pn diodes in a static random access memory cell (called hereinafter SRAM) using a thin-film-transistor (called hereinafter "TFT").
Generally, a process of manufacturing TFT in a SRAM comprises a step of forming two polysilicon layers or more which consist of a channel polysilicon layer forming channel and source/drain regions, and a gate polysilicon layer forming a gate electrode.
The top gate electrode is formed on the channel polysilicon layer and the bottom gate electrode is formed under the channel polysilicon layer.
However, forward and reverse parasitic pn diodes are formed between the channel polysilicon layer and the gate polysilicon layer.
A detailed description of parasitic pn diodes will be given below with reference to FIG. 1, FIG. 2A and FIG. 2B in which FIG. 1 is an equivalent circuit diagram of SRAM using PMOS TFT.
Referring to FIG. 1, two access transistors 1 and 2 and two driver transistors 3 and 4 are formed on a silicon substrate and two PMOS-TFT transistors 5 and 6 are formed by two polysilicon layers and a metal layer. Then, two forward parasitic pn diodes 7 and 8 and a reverse parasitic pn diode are formed in a SRAM cell.
A parasitic pn diode is formed when a p channel polysilicon layer is connected with a substrate or a polysilicon layer having many electrons such as a gate electrode of driver transistor, a n substrate, a gate polysilicon layer not a gate electrode but a pad, or the like.
Two forward parasitic pn diodes 7 and 8 appear when high voltage is applied to a channel polysilicon layer and low voltage is applied to a substrate or a polysilicon layer having many electrons. Also a reverse parasitic pn diode 9 appears when low voltage is applied to a channel polysilicon layer.
As shown in FIG. 1, an amount of electric current flowing to a high voltage node is determined by two PMOS-TFT's 5 and 6, the forward parasitic pn diodes 7 and 8 and the reverse parasitic pn diode 9. When a SRAM cell is operated, the amount of forward and reverse electric current through two parasitic pn diodes must be more large than an electric current of PMOS-TFT transistor in order to maintain a high voltage node stably. That is to say, it is desirable that an electric current of PMOS-TFT is not limited by two parasitic pn diodes.
Therefore, It is required to increase the amount of forward and reverse electric current though two parasitic pn diodes in the range of an operating voltage of TFT SRAM, particularly in a low voltage range (within 2 volt).
A conventional PMOS TFT and a metal contact will be described in detail with reference to FIG. 2.
Now referring to FIG. 2A, a conventional method forming contact between a metal layer and a TFT is to directly connect a thin channel polysilicon layer 13 with the metal layer 15. However, because the polysilicon layer 13 is made of very thin film, it may be perforated in the etching process for forming the contact hole. Accordingly, it is disadvantageous that the channel polysilicon layer 13 is only connected with a part of side surface of metal 15. Therefore, a contact between the metal layer 15 and the channel polysilicon layer 13 is unstable.
Also, in another conventional method forming contact between a metal layer and a TFT as shown in FIG. 2B, a gate polysilicon layer 11, not a gate electrode but a pad, is deposited on a first insulation film 10 and the channel polysilicon layer 13 and the metal layer 15 are connected with the gate polysilicon layer 11. In this structure, a direct bias current flows through the metal layer 15, the gate polysilicon layer 11 and the channel polysilicon layer 13. However, in this process for forming a contact between the metal layer 15 and the channel polysilicon layer 13 using the gate polysilicon layer 11, it is a problem that a reverse parasitic pn diode is formed.